| 摘要 |
There is provided a parallel processing method of logic simulation comprising representing signals on a line over a time period as a bit sequence, evaluating the output of any logic gate including an evaluation of any inherent delay by a comparison between the bit sequences of its inputs to a predetermined series of bit patterns and in which those logic gates whose outputs have changed over the time period are identified during the evaluation of the gate outputs as real gate changes and only those real gate changes are propagated to fan out gates and in which the control of the method is carried out in an associative memory mechanism which stores in word form a history of gate input signals by compiling a hit list register of logic gate state changes and using a multiple response resolver forming part of the associative memory mechanism which generates an address for each hit, and then scans and transfers the results on the hit list to an output register for subsequent use. The invention provides the segmentation of division of at least one of the registers or hit lists into smaller register hit lists to reduce computational time. Further the invention relates to a method of handling the line signal propagation by modelling signal delays.
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