Error detection and correction circuit in a flash memory

摘要

A flash memory comprises a memory sector, a command interface (3), a first signal buffer (10), a control signal generation circuit (9), a control signal generation circuit (9), a data input buffer (5), an error correction circuit (11), an address buffer (4), an address signal generation circuit (16), a plurality of data memory circuits (17), and write means (13, 14, 15). The command interface (3) receives a write data input instruction ("80"H) from an external device to generate a write data input instruction signal (INPUT), and receives a write instruction ("10"H) from the external device to generate a write instruction signal (PRO). The error correction circuit (11) is activated by the write data input instruction signal (INPUT) to receive the write data in synchronization with the write enable signal (nWE), and is activated by the write instruction signal (PRO) to generate a check data for an error correction in synchronization with the control signal (CGCLK). With this configuration, processing to generate the check data for the error correction with the internal error correction circuit and processing to input the check data to the write circuit, etc. can be automatically performed in the flash memory even in the period when the external control signal is not input.