Method for optimizing test fixtures to minimize vector load time for automated test equipment

摘要

A systematic method for assigning tester channels on an Automated Test Equipment (ATE) to various signal pins on Device Under Test (DUT). The method involves creating a test fixture or a load board for a digital Integrated Circuit (IC) by wiring the DUT pins to as few channel groups as possible. The number of channel groups required for each vector set load are calculated before the signal pins are assigned. Then, the signal pins are assigned in a systematic manner to the fewest number of channel groups. As the number of test channel groups is reduced, the amount of vector data loaded into the tester's vector memory before each test vector is executed also is reduced, therefore reducing the time and cost required to test the signal pins on the DUT.