Circuit and method for selectively delaying electrical signals

摘要

A circuit and method for selectively and dynamically delaying a signal is presented. A series of delay modules are used to provide progressively finer delays. A multiplexer is used after each delay module to select one of a plurality of signals to pass on to a subsequent delay module. Each multiplexer is controlled by a control signal which can vary in time so that different delays can be selected for different portions of the signal to be delayed. By providing the proper control signals to the multiplexers any delay corresponding to a sum of the available individual delays generated by the individual delay modules is possible. The circuit and method are particularly useful for imposing individual delay times on the pulses in a logic level signal.