| 摘要 |
A microprocessor with an execution stage (26) including a plurality of execution units and an instruction memory (32) for storing instructions. The microprocessor further includes circuitry for retrieving (14) instructions from the instruction memory. This retrieving circuitry may retrieve one instruction simultaneously with the execution of another instruction by one of the plurality of execution units. Further, this retrieving circuitry includes a branch target memory (30) for storing a plurality of information fields (30r) corresponding to a branch instruction. The information fields include at least a target instruction address (Tn), a prediction field (Pn) indicating whether or not program flow should pass to the target instruction address, and an accuracy measure (PPAn) indicating accuracy for past prediction fields. In operation, the circuitry for retrieving instructions retrieves (46), as a next instruction to follow the branch instruction, an instruction corresponding to the target instruction address in response to a function (TPn) responsive to the accuracy measure exceeding a predetermined threshold and the prediction field indicating program flow should pass to the target instruction address. Additionally, the circuitry for retrieving instructions retrieves (54), in response to the function responsive to the accuracy measure not exceeding a predetermined threshold, a first group of instructions, wherein the first group of instructions is sequentially arranged after the branching branch instruction and includes an instruction corresponding to the target instruction address.
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