| 摘要 |
There is provided a multi-bank-structured DRAM capable of high-speed data transfer without enlarging the chip size due to increase of the line width of power source lines and addition of internal power source generation circuits. In a multi-bank-structured DRAM, cell array units forming each bank are assigned divisionally to cell array units in both sides of an interface circuit interposed therebetween. This division of cell array units is carried out such that those units that are positioned point-symmetrically with respect to the center of the interface circuit are selected and are assigned to one same bank. As a result, the layout of internal power source circuits in the interface circuit can be designed in match with half of power dissipation of the chip. The line width of power source lines can therefore be reduced to small. The chip size can also be reduced by dividing the power dissipation into independent internal power source generation circuits in accordance with the division of the cell array units.
|
