| 摘要 |
A method for controlling a high speed memory unit M to be read from, and written to, as initiated by clock signals of comparable speed, this method involving: providing a timing coordinator unit with bi-stable store for storing and presenting certain input signals to the memory unit in conjunction with the clock signals so as to be immediately useable thereby and so that the memory unit can responsively output data to a user stage; these input signals being arranged to include commands R/W to Read or Write, Address signals and Data signals; and the memory unit being maintained in "ready-to-read" condition at all times except during receipt of write commands.
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