IMPROVED IC DESIGN FLOORPLAN GENERATION USING CEILING AND FLOOR CONTOURS ON AN O-TREE STRUCTURE

摘要

An EDA tool is provided with a floorplan generator to automatically generate an optimized floorplan for an IC design having a number of design blocks. The floorplanner generates an initial O-tree representation for the design blocks. The floorplanner then perturbs the O-tree representation to seek an alternate O-tree representation that represents an optimized placement of the design blocks in accordance with a cost function. The floorplanner performs the perturbation systematically for all design blocks, traversing the O-tree representation in a depth-first manner and removing one design block at a time. In one embodiment, for each removed block design, the floorplanner also seeks an appropriate re-insertion point for the removed design block systematically by traversing a reduced version of the O-tree representation augmented with candidate insertion points in a depth-first manner. Under the present invention, ceiling and floor contours as well as contour pointers are employed to improve the efficiency of the traversing iterations.