| 摘要 |
<p>A flash memory comprises an address bus (40), a data bus (50), control lines, and an array (64) of addressable non-volatile memory cells, connected to the address bus (40) and the data bus (50). A latch (52, 54), activated by control signals, stores signals supplied from the address bus (40) or the data bus (50). A decoder (56) decodes the signal stored in the latch (52, 54), and in response to a first signal operates to partition the array (64) of memory cells into a plurality of first sectors each having a first size, and in response to a second signal operates to partition the array (64) of memory cells into a plurality of second sectors each of a second size, different from the first size. Control circuitry (70) controls the erasure of a first or a second sector of the memory array (64) in response to the first or second signal decoded. <IMAGE></p> |
