SEMICONDUCTOR DEVICE SIMULATION METHOD AND SIMULATOR

摘要

An automated simulation method for determining the enhanced generation-recombination rate due to trap-to-band tunnelling in a semiconductor device using the Dirac coulombic tunnelling integral and to a simulator for carrying out the method are disclosed. The method and simulator are, for example, particularly useful in the modelling of characteristics such as leakage current in polysilicon TFTs, which leakage current can, for example, seriously degrade pixel voltage in active matrix display devices. The simulator embodies the method, which method comprises the steps of: assigning the variable C to the ratio of the Poole-Frenkel barrier lowering energy (ΔEfp) divided by the energy range for which tunnelling can occur (ΔEn); assigning the value (C+1)/2 to a variable v and performing a second order Taylor's series expansion of the Dirac coulombic tunnelling integral around v to determine a maximum value (umax) for the variable u of the integral; determining if the value for umax is less than C, is between C and 1 or is more than 1; assigning the value of C to the variable v if umax is less than C; assigning the value of umax to the variable v if umax is between C and 1; assigning the value of 1 to the variable v if umax is more than 1; reducing the Taylor's series expansion of the Dirac coulombic tunnelling integral to an error function; reducing the error function to simple exponential functions by applying rational approximations to the error function; and calculating the enhanced generation recombination rate due to trap-to-band tunnelling in a semiconductor device using the said simple exponential functions.