| 摘要 |
Two source/drain regions (12, 22, 32) between which a channel region is arranged are provided for in a semiconductor substrate (11, 21, 31). A gate dielectric comprising a dielectric intermediate layer (13, 23, 33) and a dielectric structure (14, 24, 34) is positioned on the surface of the channel region. The dielectric structure (14, 24, 34) borders on the dielectric intermediate layer (12, 22, 32) on at least one side which is directed towards one of the source/drain regions (12, 22, 32), whereby the thickness of the gate dielectric above the edge of the source/drain region is greater than the thickness of the dielectric intermediate layer. |
