| 摘要 |
An integrated circuit two-stage power amplifier provides a high-voltage, series-biased FET amplifier for high-efficiency applications. An input is connected to an input matching network, and a driver cell provides power from the input matching network to an interstage power dividing network. Multiple similar cells in a second stage are connected between the interstage power dividing network and an output matching and combining network and are biased by a series-connected active biasing network. An output is connected to the output matching and combining network. One series-connected active biasing network includes series-connected resistances and a second string of series-connected buffer cells connected between the series-connected resistances and the RF power cells for biasing the RF cells. TABLE 1- State-of-the-Art, Ka-band MMIC Results - Freq. Power Gain PAE BW Chip - (GHz) (W) (dB) (%) (GHz) #Stg. Voltage - 33 0.66 16.2 41.1 2.7 2 20 - 33 1.12 12.5 35.8 2.5 2 28 - 30 0.5 8.5 32.3 6 2 4 - 35 1.3 9 24 2 2 5 - 36 0.22 20 21.5 4 3 6 - 40 1.0 9 29.4 6 2 4 -
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