| 摘要 |
PCT No. PCT/FR97/00035 Sec. 371 Date Jul. 9, 1998 Sec. 102(e) Date Jul. 9, 1998 PCT Filed Jan. 9, 1997 PCT Pub. No. WO97/25668 PCT Pub. Date Jul. 17, 1997A modular arithmetic coprocessor designed to perform computations according to the Montgomery method includes a division circuit to perform integer divisions. The integer division circuit computes the division of a binary data element A encoded on n+Z +n (bits by a binary data element B encoded on n bits, A, B, n, n' and n'' being on-zero integers. For this function, the integer division circuit includes: a first n-bit register and a second n-bit register to contain the binary data element A and the result of the division, a third n-bit register to contain an intermediate result, a fourth n-bit register to contain the binary data element B, two subtraction circuits each having a first series input and a second series input and a series output, and a test circuit having an input and an output.
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