发明名称 System level IC testing arrangement and method
摘要 A method and apparatus for testing an integrated circuit in a system level environment such that the integrated circuit to be tested is wired into a system or module when the testing occurs is disclosed. In one embodiment of a method aspect of the invention, a die in a packaged integrated circuit to be tested is exposed. A module that incorporates the exposed die is placed on a test platform. The test platform and a sensor probe are relatively positioned such that the sensor probe can directly monitor the exposed die during testing. The positioning may be accomplished by moving the test platform, the sensor probe or both. The system is then driven in a manner which exercises the exposed die. The sensor probe then directly monitor the die while the exposed die is being exercised. The die can be exposed in a variety of manners as for example by removing a package cover or by etching portions of the plastic packaging material. An integrated circuit tester suitable for implementing this process is also disclosed as well as a test board suitable for use when the integrated circuits being tested are cavity down packaged integrated circuits.
申请公布号 US6163866(A) 申请公布日期 2000.12.19
申请号 US19940282913 申请日期 1994.07.29
申请人 SUN MICROSYSTEMS, INC. 发明人 ANSARI, SHAHID S.
分类号 G01R31/26;G01R31/00;G01R31/28;G01R31/319;H01L21/66;(IPC1-7):G01R31/28 主分类号 G01R31/26
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