| 摘要 |
PROBLEM TO BE SOLVED: To provide a device and a method for accessing a memory core two times or more in one clock cycle using self-timing logic. SOLUTION: A one time access memory core 30 is coupled to a memory wrapper using a memory wrapper 28 in which self-timing logic 36 and a multiplexer 32 are incorporated. A memory interface device 10 connects a central processing unit 12 to the memory wrapper. When self-timing logic is connected to an access memory wrapper plural times, compensation is not required. Also, as self-timing architecture separates between environment (what is clocked in a system clock) and access for a core, access can be performed with the speed of a core processing plural times in one cycle of a system clock. This device and method can be incorporated in a digital signal processor and a transmitter/receiver for a digital cellular telephone. |
