Data processor

摘要

A data processor including an alternative clock generator for generating, in a power saving mode, an alternative clock signal which is supplied to a peripheral circuit instead of a system clock signal. This enables only the peripheral circuit such as an A/D converter to be put into operation in response to the alternative clock signal in the power saving mode. This solves a problem of a conventional data processor in that it cannot achieve the power saving efficiently because it is unavoidable for the remaining portion of the conventional data processor like a CPU to be involved in a high-rate operation along with the peripheral circuit even if it is desired to operate only the peripheral circuit at a high-rate when releasing the sleep mode or changing the sleep mode to a high-rate mode.