| 摘要 |
A combination vertical MOSFET and JFET device (18,22) is formed in a mesa (20,24) of semiconductor material. A top gate (44,68) of the device is formed by creating a preferably annular trench (36,58) that extends downwardly from the surface of the semiconductor layer, creating a thin gate insulator (41,62) on the bottom and sidewalls of this trench, and filling the trench with highly doped polysilicon. A buried gate region (28,50) is formed by implanting the semiconductor layer, prior to top gate formation, such that the buried gate region is laterally coextensive with the mesa. An upper boundary (29,54) of the buried gate region is spaced below the bottom of the trench and spaced from the semiconductor surface. Upon application of a suitable voltage, the buried gate region and the top gate region coact to invert the conductivity type of the channel region, permitting transistor operation between the source region and the drain region.
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