Methods and systems for column line selection in a memory device

摘要

An integrated circuit device is provided having a column selection circuit which activates the column selection line output responsive to a column latch signal rather than a data command signal. The leading edge of the column latch signal is used to generate a master clock signal and to latch the selected address. The master clock signal is delayed and a column decoder circuit decodes the latched selected address to activate the appropriate column selection line output responsive to the delayed clock. As activation of the column selection line output initiates placement of the desired sense amplified bit line signal on the local input and output lines, the voltage differential on the local input and output lines can begin to develop earlier than with the prior art approaches. Therefore, the voltage levels on the local input and output lines may reach the desired levels before or shortly after the data command signal is activated thereby allowing the input and output sense amplifier to be enabled and output the read data shortly after the data command signal is activated. Write operations may be similarly supported. Methods are also provided.