发明名称 SYSTEM CLOCK SYNCHRONIZING DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To automatically adjust the phase of the clocks of duplex systems by receiving the clock from the other system, detecting the phases of the clocks of the self-system and the other system and setting clock delay quantity by means of a CPU. SOLUTION: The clock of the other system is inputted to a detection circuit for phase adjustment 30 through a buffer 9b. The output clock of a selector 7 is inputted and the phase difference of the clocks on the self-system and the other system is detected. A CPU 2 receives the phase difference, controls a clock control circuit 3 and gives selection signals to decoders 4c and 6c. The decoder 4c selects a necessary delay element in accordance with the phase difference from delay elements 4a and sends delayed clocks to the self-system and the other system. The same processing is executed in the system 1. The outputs of the detection circuits for phase adjustment 30 and 31 are inputted to devices to be synchronized 20 and 21.</p>
申请公布号 JP2000353026(A) 申请公布日期 2000.12.19
申请号 JP19990162543 申请日期 1999.06.09
申请人 FUJITSU LTD 发明人 SATO KAZUYUKI
分类号 G06F1/04;G06F1/10;(IPC1-7):G06F1/04 主分类号 G06F1/04
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