发明名称 METHOD AND DEVICE FOR SIMULATING FAULT IN LOGICAL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce faults to be simulated as much as possible and to quickly execute fault simulation. SOLUTION: In a logical circuit fault simulation device 10 for simulating the normal operation and fault operation of a logical circuit, a fault generation part 42 selectively uses a logical cell model suited to fault generation and a fault simulation execution part 43 selectively uses the logical cell model suited to the description of a logical function. Consequently an effect for improving the generality of fault compression processing can be obtained.
申请公布号 JP2000353185(A) 申请公布日期 2000.12.19
申请号 JP19990164497 申请日期 1999.06.10
申请人 SHARP CORP 发明人 MATSUMOTO TOSHIYUKI
分类号 G01R31/28;G06F11/26;G06F17/50;(IPC1-7):G06F17/50 主分类号 G01R31/28
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