| 摘要 |
A self-timed latch circuit according to the present invention includes a first inverter for inverting a set signal, a second inverter for inverting a reset signal, a first main driver driven by an output signal from the second inverter and the set signal, a second main driver driven by an output signal from the first inverter and the reset signal and a static latch cross-coupled with first and second output terminals of the first and second main drivers. The self-timed latch circuit according to the present invention reduces the power consumption and increases the operation speed of the circuit by removing a back-to-back connection and a serial connection of transistors applied to the conventional art. Further, since the static latch consists of cross-coupled inverters, the self-timed latch circuit according to the present invention prevents signal fighting during the logic transition of output signals and also reduces a leakage current generated during the operation of the circuit.
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