| 摘要 |
A method for manufacturing a low voltage high frequency silicon power transistor applying epitaxial mesa structure using a minimized number of masks has a highly doped silicon n++ substrate forming the emitter. Also a low voltage high frequency silicon transistor chip presenting an epitaxial mesa technology silicon power device is presented. The silicon transistor layout presents a collector-up device with a number of single mesa collector structures. The transistor operates with its substrate as a down facing emitter, and base and collector areas together with bonding pads facing up, whereby the parasitic base-to-collector capacitance is almost entirely eliminated with the emitter as substrate. The reduced number of necessary fabrication process steps of this new structure is outlined. |
