发明名称 |
PACKETIZED ELEMENTARY STREAM RECONSTRUCTION APPARATUS FOR INTERFACE BETWEEN ENCODER AND MULTIPLEXER |
摘要 |
PURPOSE: A PES(packetized elementary stream) reconfiguration device for interface between an encoder and a multiplexer is provided to simplify control circuit and to stabilize system operation by correcting system timing clock data error generated in the transfer from the encoder to the multiplexer. CONSTITUTION: An extractor(31) extracts an elementary bit stream clock reference data from a PES input from an encoder. A clock generator(34) generates a time stamp data. A comparator(33) compares the elementary bit stream from the extractor(31) and the time stamp data from the clock generator(34) and outputs the difference. A reconfigurator(32) constructs packetized elementary bit stream from the extractor(31) and corrects the decoded time stamp data by the difference value input from the comparator(33).
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申请公布号 |
KR100275531(B1) |
申请公布日期 |
2000.12.15 |
申请号 |
KR19970064108 |
申请日期 |
1997.11.28 |
申请人 |
KOREA TELECOM;KOREA ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
LEE, HAN KYU;KIM, JIN WOONG;KIM, JAE GON |
分类号 |
H04L9/00;(IPC1-7):H04L9/00 |
主分类号 |
H04L9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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