TIME DELAY COMPENSATION CIRCUIT IN CLOCK BUFFER

摘要

PURPOSE: A circuit for compensating for delay time of clock buffer is provided to compensate promptly for delay time of clock buffer by using time interval extraction chain and variable delay time chain. CONSTITUTION: A toggle flipflop(20, 21) divides frequency of input clock signal and delay clock signal to 1/2, and relaxes condition of input clock signal that must have 50% duty rate. A time interval extraction chain(22) which consists of several time interval extraction cells(TS1-TSn) extracts time interval from rise edge of input clock signal to rise edge of delay clock signal. A variable delay time chain(23) which consists of several variable delay time cells(DS1-DSn) delays input clock signal for the time interval extracted by the time interval extraction chain(22).