APPARATUS AND METHOD OF PROCESSING HIGH SPEED CELL SEQUENCES FOR MULTI-PATH ASYNCHRONOUS TRANSFER MODE SWITCH

摘要

PURPOSE: An apparatus for processing high speed cell sequences for a multi-path asynchronous transfer mode(ATM) switch is provided to compare cell sequences only included in same per-VC logical queue by virtual channel identifier(VCI) information and time stamp information, so as to improve operation speeds. CONSTITUTION: An input cell register(ICR)(11) temporarily stores an inputted cell in an input stand-by state. The inputted cell is stored in a RAM buffer and is extracted. A content addressable memory(CAM)/RAM table(14) stores virtual channel identifiers(VCIs) of each VC logic queue and an address of a RAM buffer(13). The RAM buffer stores first cells of each logic queue. A controller(15) controls input/output processes of the RAM buffer, and compares a time stamp value of the inputted cell with a time stamp value of a cell of the RAM buffer. A VCI shift register(VSR)(12) receives a VCI from the inputted cell and supplies the VCI to the controller. In a cell outputting process, a VCI value of the VSR is supplied to the controller. If a newly-inputted cell arrives, an idle address pool(IAP)(16) supplies an idle address of the RAM buffer to the controller.