| 摘要 |
PURPOSE: A level shifting circuit is provided to reduce power consumption due to standby current by removing a direct current path of a ground terminal from a high voltage power terminal. CONSTITUTION: A level shifter circuit includes first, second and third PMOSs(21,22,23) whose gates receive clamping bias in common, first and second NMOSs(24,25) serially connected to the first and second PMOSs respectively whose sources are connected to the ground and whose gates receive a non-inverted first input signal and inverted first input signal, respectively, and a third NMOS(26) which is connected to the drain of the third PMOS and an output port and receives a second input signal to its gate. The level shifter circuit also has fourth and fifth PMOSs(27,28) selectively turned on or off by turning on the first NMOS or second NMOS to restrict standby current from flowing, first and second zener diodes(29,30) connected between the drains of the fourth and fifth PMOSs and VDDH in common to prevent the drain voltages from being decreased below a predetermined level, and a sixth PMOS(31) connected to the third PMOS in cascade whose gate is connected to the gate of the fourth PMOS and the drain of the fifth PMOS in common to pull up the output level of the output port to VDDH level.
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