APPARATUS FOR GENERATING QUAD CLOCK SIGNAL IN RAMBUS DRAM

摘要

PURPOSE: An apparatus for generating a quad clock signal in a RAMBUS DRAM is provided which reduces the skew difference between a quad clock signal and an inverted quad clock signal as reducing the size of a circuit by simplifying the circuit. CONSTITUTION: An apparatus for generating a quad clock signal in a RAMBUS DRAM comprises: the first phase separation part(40) which generates a delayed clock signal by delaying an input clock signal and generating an inverted clock signal by inverting a phase of the delayed clock signal; an output selection part(42) which generates a power source voltage(or a ground voltage) in response to the delayed clock signal and outputs a ground voltage(or a power source voltage) in response to the inverted clock signal; an output driving part(44) amplifying the signal generated in the output selection part; a buffer(46) generating a quad clock signal by buffering the signal generated in the output driving part; and the second phase inversion part(48) which delays the quad clock signal generated in the buffer and generates it as a synchronous clock signal, and inverts the synchronous clock signal and generates it as an inverted synchronous clock signal. Therefore, the apparatus reduces the variation of a setup hold time(tSH) and a data output time(tQ) between pins by reducing the size of the circuit.