| 摘要 |
PROBLEM TO BE SOLVED: To obtain a PLL circuit that is made stably earlier to a target frequency when a device employing the PLL circuit enters an operating state from after application of power or from a pause state. SOLUTION: The PLL circuit is provided with a PLL oscillation circuit 1 that has a VCO 2 and a phase comparator circuit 4 and uses a PLL loop generating a control voltage for the VCO 2 in response to the result of phase comparison to produce an output whose frequency is locked to the clock frequency and with a boost-up circuit 11 in addition to the circuit 1. The circuit 11 receives a clock signal from an input terminal 8 and an oscillation signal from the VCO 2 and transits the control voltage in a direction of increasing the frequency to reach a prescribed oscillated frequency when the frequency of the oscillated signal is less than a latter limit of the frequency setting range and adds a signal operated in a direction of correcting the frequency even when the frequency of the oscillated signal exceeds an upper limit or generates the signal to the PLL loop and stops the operation of the PLL loop when the frequency is resident within a prescribed range. This range is selected so that it is smaller than a range of first increasing or decreasing fluctuation of fluctuated ringing in the oscillated signal. |
