发明名称 DEVICE AND METHOD FOR SUPPORTING GATED CLOCK DESIGNING
摘要 PROBLEM TO BE SOLVED: To design a circuit which has a higher power-saving effect by generating enable logic while taking don't-care conditions into account. SOLUTION: The enable logic which is controlling a storage element taken out of a circuit stored in a circuit information storage part 1 is stored in an enable logic information storage part 3 extracted by an enable logic extraction part 2. An enable logic expansion candidate extraction part extracts the minimum term having the largest signal value probability found by a signal value probability calculation part 5 for respective minimum terms included in an ON set of the stored enable logic. A don't-care condition inquiry part 6 inquires whether the taken-out minimum term meets the don't-care conditions of a user through a user interface 8 and moves this minimum term from the ON set to an OFF set when the minimum term meets the conditions. After all the minimum terms included in the ON set are processed, an enable logic update part 7 updates the enable logic according to the new ON set.
申请公布号 JP2000348080(A) 申请公布日期 2000.12.15
申请号 JP19990158230 申请日期 1999.06.04
申请人 TOSHIBA CORP 发明人 KITAHARA TAKESHI
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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