TEST MODE ENTERING CIRCUIT

摘要

PURPOSE: A test mode entering circuit is provided to drive a test circuit without needing a test terminal by connecting the test mode entering circuit to a user terminal. CONSTITUTION: A test mode entering circuit comprises the first logic sum circuit(10) which consists of a plurality of AND gates having input terminals connected to user terminals. The third logic sum circuit(14) receives output signals from the first and second logic sum circuits(10,12) to output a plurality of clock signals(tclk0-tclk4). A D flipflop circuit(16) is cleared by a reset signal provided through an inverter(17), and receives the clock signals(tclk0-tclk4) to output a test mode signal(TSTMOD) to a test circuit(18).