发明名称 PATTERN LAYOUT INSTRUCTION SYSTEM
摘要 PROBLEM TO BE SOLVED: To automatically verify whether or not an instruction presented by a circuit designer matches a final layout drawing by inputting and storing layout drawing data in a pattern layout instruction system. SOLUTION: For a database (S21) for circuit plans, a computer for CAD switches a menu of input mode to select a layout instruction mode (S22) and inputs a layout instruction from a keyboard to generate circuit plan data and layout instruction (S23, 24). A layout is made according to the generated circuit plan data and layout instruction data to generate data of a layout drawing (S25, 26). Then the data of the generated layout drawing and original layout instruction data are used by a computer to automatically verify whether or not both of then match each other (S27, 28+). If there is an element, a wire, etc., which do not match, their contents are displayed on a screen and outputted as a list (S28 to 30).
申请公布号 JP2000348074(A) 申请公布日期 2000.12.15
申请号 JP19990155417 申请日期 1999.06.02
申请人 SONY CORP 发明人 IWANAGA HIROHISA
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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