发明名称 SUBSTRATE PROCESSOR
摘要 PROBLEM TO BE SOLVED: To secure a work area in a processing station, while the processing station is miniaturized, for example, in an application/development device. SOLUTION: A processing station S2, for applying resist and heaping developer, is connected to a cassette station S1 to/from which a wafer cassette 22 is carried. In the station S2, a first processing unit U1 an antireflection film forming unit 3 and an application unit 4 arranged in two stages is installed on the left side as seen from the cassette station S1, a second processing unit U2 where a developing unit 4 and a peripheral edge aligner 7 are arranged in two stages, so that it faces the first processing unit U1 is installed on the right side and respective two wafer transfer means MA1, MA2, MA3 and MA4 are arranged in regions facing the row of the processing units U1 and U2. In such layout, a work area can be secured in the area between the first and second processing units U1 and U2.
申请公布号 JP2000348995(A) 申请公布日期 2000.12.15
申请号 JP19990154056 申请日期 1999.06.01
申请人 TOKYO ELECTRON LTD 发明人 UEDA KAZUNARI
分类号 H01L21/306;C23F1/08;H01L21/00;H01L21/027;H01L21/30;H01L21/677;(IPC1-7):H01L21/027 主分类号 H01L21/306
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