| 摘要 |
PROBLEM TO BE SOLVED: To permit address information transfer on a bus for data transfer by dividing a direct memory access(DMA) cycle into a DMA cycle for reporting an address to be accessed in the next DMA and DMA for transferring data, and controlling the transfer of that DMA with the address. SOLUTION: A DMA request address and DMA request data from an external connection device 4 are supplied to a DMA transfer request circuit 3 and divided into address information, data information and data transfer direction. Concerning a DMA data transfer request using a bus 7, that DMA transfer request circuit 3 distinguishes whether the address requested by the external connection device 4 is to be transferred or write or read is to be performed to that address. Thus, an address data discriminate signal and a data transfer direction signal are respectively generated on signal lines 9, 10 and 11 together with the DMA request signal and outputted to a DMA transfer accepting circuit 2 and DMA transfer is controlled.
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