SEMICONDUCTOR MEMORY DEVICE WITH TRIPLE WELL STRUCTURE AND MANUFACTURING METHOD THEREFOR

摘要

PURPOSE: A semiconductor device having a triple well structure is provided to improve a noise characteristic and the speed without increasing the layout size by separating a P type well into an NMOS of a P type well and an NMOS of a P type well. CONSTITUTION: The semiconductor device includes the first N type well(304) formed on a semiconductor substrate(302), and the first P type well(306) formed on the first N type well(304). The first N region(308) and the first gate(310) each becoming a source/a drain, and the first P type region(312) connected to a back bias voltage(VBB) terminal are formed on the first P type well(306). The second N region(316) formed on the second P type well(314) and the second gate(318), each becoming a source/a drain, and the second P type region(320) connected to a ground voltage(VSS) terminal are formed on the first N type well(304). A memory array is formed on the first N type well(304). The memory array consists of the third P type region(322) and the third gate(324), each becoming a source/a drain, and the third N region(326) connected to a supply power voltage(VCC) terminal. The semiconductor memory device includes the third P type well(315) on the P type substrate(302). The firth N type region(330) and the fourth gate(332), each becoming a source/a drain, and the fourth P type region(334) connected to the ground voltage(VSS) terminal are formed on the third P type well(315). The second N type well(305) is formed on the P type substrate(302). The fifth P type region(338) and the fifth gate(340), each becoming a source/da rain, and the fifth N region(342) connected to the power supply voltage(VCC) terminal are formed on the second N type well(305). The sixth P type region(344) connected to the ground voltage(VSS) is formed on the P type substrate(302).