| 摘要 |
PURPOSE: A detection and malfunction preventing circuit is provided to perform a stable inverter operation by varying the level of an interrupt signal after delaying for a predetermined time period upon detecting that a switch is pressed. CONSTITUTION: A signal delaying block(12) outputs function selecting signals(V1-V3) to a microcomputer(14) in response to the selection of switches(SW1-SW3) by a signal switching block(11). An interrupt block(13) maintains the level of an interrupt signal(INT) outputted to the microcomputer(14) in response to the logical operation of the outputs(V1-V3) of the signal delaying block(12), and has an AND gate(AN1), a clock generating block(15), inverters(IN1,IN2) and an OR gate(OR1). The AND gate(AN1) logically multiplies the outputs(V1-V3) from the signal delaying block(12). The clock generating block(15) outputs a high-potential signal(V5) in response to a low-potential output(V4) of the AND gate(AN1). The inverters(IN1,IN2) buffer the output(V4) of the AND gate(AN1). The OR gate(OR1) logically sums the output(V5) of the clock generating block(15) to output the interrupt signal(INT).
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