| 摘要 |
<p>PROBLEM TO BE SOLVED: To transfer data with high accuracy, high responsiveness and at high speed by suppressing the variance of data delay time when the parallel data are transferred at high speed. SOLUTION: An F/F 3 holds a single bit of data synchronously with a sending side clock and an F/F 4 generates a source clock from the sending side clock. A wire address generation circuit 11 generates a write address signal from the source clock. A write selector 10 selects the single bit of data according to the write address signal, and a data holding circuit 12 samples the single bit of data via the source clock. A read address generation circuit 15 inputs a synchronizing signal from a synchronizing circuit 14 and generates a read address signal that is synchronized with a receiving side clock. A read selector 13 outputs the signal bit of data of the circuit 12 according to the read address signal. Then an F/F 17 samples the single bit of data via the receiving side clock and outputs it.</p> |
