发明名称 INTEGRATED MEMORY AND OPERATING METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To make generable a reference voltage in a comparatively short time by a method wherein a first switching element which is used to connect two bit lines and a selection transistor for two reference memory cells are turned on, only the selection transistor is turned off after a prescribed period, and the potential difference between the two bit lines is offset. SOLUTION: A first switching element S1 which short-circuits a first and second bit lines BL1 and the inverse of BL1, and a selection transistor for two reference memory cells RCs are turned on by a control unit C1. After a prescribed period has elaped, the first switching element S1 is continuously set to continuity, and the potential difference between the bit lines BL1 and the inverse of BL1 is offset. Consequently, the influence of the nonlinear memory capacitor of the reference memory cells RCs on a reference voltage is smaller than that, in a case where the selection transistor is set to continuity up to the perfect equilibrium of an electric charge between the bit lines BL1 and the inverse of BL1.
申请公布号 JP2000348485(A) 申请公布日期 2000.12.15
申请号 JP20000143734 申请日期 2000.05.16
申请人 INFINEON TECHNOLOGIES AG 发明人 SCHLAGER TOBIAS;MANYOKI ZOLTAN;ESTERL ROBERT
分类号 G11C14/00;G11C11/22;G11C11/409;G11C11/41;(IPC1-7):G11C11/22 主分类号 G11C14/00
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