| 摘要 |
The point memory has two independent inputs (IN1, IN2) and one output (OUT), and comprises two inversion branches (IB1, IB2) connected between a supply voltage (Vcc) and a reference voltage (VRef). The first inversion branch (IB1) comprises two MOS transistors (TP1, TN1) of opposite conductivity type connected in series drain-drain with the gate of one transistor connected to one independent input (IN1). The second inversion branch (IB2) also comprises two MOS transistors (TP2, TN2) connected in series drain-drain with the gate of one transistor connected to the other independent input (IN2). The joining drain-drain point of the first branch is connected to the gate of the second transistor (TN2) of the second branch, and the joining drain-drain point of the second branch, which is the output, is connected to the gate of the first transistor (TP1) of the first branch, forming a feedback loop. In the second variant of the point memory, the gate of the first transistor of the first branch is connected to the first input, and the gate of the second transistor of the second branch to the second input; the feedback loop is formed by connecting the output to the gate of the second transistor of the first branch. In the third variant of the point memory, the first branch comprises an auxiliary MOS transistor of the same conductivity type as the first MOS transistor, which is connected in series drain-source, and the gate is connected in parallel to that of MOS transistor of opposite conductivity type, to enhance the insensitivity of circuit to impact of ionizing particles. A memory cell is formed by connecting two identical point memories of the first or second variants by connecting the output of the first, respectively second, point memory to the gate of MOS transistor of the first branch of the second, respectively first, point memory, and by connecting the joining drain-drain point of the first branch of the first, respectively second, point memory to the gate of MOS transistor of the second branch of the second, respectively first, point memory. A memory cell also comprises means for writing a logic state at the level of first or second point memory, where the writing means comprise a first inverter receiving a clock signal and delivering an inverted clock signal, a second inverter receiving the logic state and delivering an inverted logic state, first and second ports controlled by the clock signal and the inverted clock signal, the first and second ports receiving the inverted logic state and delivering it to the independent input connected to the gate of the first MOS transistor of the second branch of the first, respectively second, point memory. The first branch of the first and second point memories comprises a buffer MOS transistor connected in series drain-source with the first, respectively second, MOS transistor constituting the first branch.
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