A 16 BIT PARALLEL HEC ENCODER

摘要

PURPOSE: A 16-bit parallel header error correction incoder is provided to enable process in low rate and prevent loss of electric power in device which generates HEC(header error correction) of ATM(automatic teller machine) cell header 4 byte by generating CRC(cyclic redundance check) of ATM cell header 4 byte of 622Mbps transmission rate and processing in 16-bit parallel in inserting into fifth byte. CONSTITUTION: An operation circuit unit(EX1) is operated by enable signal, and outputs inputted data(100) which is read by 4 head and receives inputted result of register group, and outputs HEC result operated in logic combination in 8 bit. A flipflop(D1) enables the 8-bit HEC value operated in the operation circuit unit(EX1) to be inputted in fifth byte after header 4 byte. An enable signal generating unit generates enable signal fitting for the fifth byte.