| 摘要 |
PROBLEM TO BE SOLVED: To enable verification in detailed timing while holding a simulation speed almost at an algorithm level by detailing the range of a specific test pattern and a specific part of an object to be verified into a lower verification level. SOLUTION: An algorithm simulator 7 inputs a test pattern 5 and design data 1 of the top verification level and verification of the top level is performed for the whole circuit, and the simulation result is outputted and held as an algorithm simulation result 8. A delay information extracting means 9 analyzes the structure of the verification object and provides delay values obtained in time-series units of individual verification levels in all combinations of condition decision making from inputs of the respective verification levels to respective signals and delay information 10 for finding them. A simulation result detailing means 11 details the simulation result on the basis of the delay information 10 in time-series units of the verification levels for detailing the time series of simulation result while using the detailing parameters of the verification of detailing control data 6 as conditions.
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