EQUALIZER AND DE-EQUALIZER WITH 16 BIT PARALLEL SELF-SYNCHRONIZATION

摘要

PURPOSE: A 16-bit parallel self-synchronous mixer and reverse mixer is provided to enable process in low rate and prevent loss of electric power by generating CRC(cyclic redundance check) of ATM cell header 4 byte of 622Mbps transmission rate and processing in 16-bit parallel in inserting into fifth byte. CONSTITUTION: It consists of 16-bit parallel register and 6-bit parallel exclusive OR-gate. Several registers(10) are laid out in parallel by sixteen, and result shifted sixteen times in one clock is output. An exclusive OR-gate(30) is laid out in parallel by sixteen too, and receives output signal of previous state of the several registers(10) and 16-bit parallel input data row, and performs exclusive logic addition to generate mixed 16-bit parallel output data row.