发明名称 VARIABLE LENGTH DECODING AND METHOD FOR DECODING TWO CODES PER CLOCK CYCLE
摘要 Apparatus and method for determining the lengths of a plurality of variable length encoded data values included in a data stream within a single clock cycle. The apparatus includes a shifter for receiving the data stream. The shifter is responsive to a shift control signal for transmitting a subset of the plurality of variable length encoded data values. A first length decoding mechanism is coupled to receive the subset of the plurality of encoded data values. The first length decoding mechanism performs a first decoding operation to determine the length of a first one of the encoded data values in the subset. A second length decoding mechanism is also coupled to receive the subset of the plurality of encoded data values. The second length decoding mechanism performs a second decoding operation to individually determine the length of a second one of the encoded data values in the subset. The second encoded data value immediately follows the first encoded data value in the subset. The first and second decoding operations are performed simultaneously. A combined length decoder is responsive to the lengths of the first and second encoded data values for outputting a combined length of the first and second data values. A shift controller forms the shift control signal in response to the combined length of the first and second data values. The shift control signal identifies a position of a next encoded data value within the shifter. The next encoded data value immediately follows the second encoded data value. The shift controller transmits the shift control signal to the shifter. <IMAGE>
申请公布号 KR100276037(B1) 申请公布日期 2000.12.15
申请号 KR19970011402 申请日期 1997.03.29
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 SITTA, RICHARD;BROSZ, EDWARD M
分类号 H04N7/30;H03M7/40;H03M7/42;H04N1/41;H04N7/50;(IPC1-7):H04N7/24 主分类号 H04N7/30
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