Voltage buffering arrangement in dynamic CMOS memory, i.e. DRAM

摘要

The arrangement includes a p-conductive semiconductor substrate (7), an n-conductive tub structure (5, 6) provided in the semiconductor substrate, a p-conductive semiconductor area (4) included by the tub structure, and an NMOS transistor (1) provided in the p-conductive semiconductor area. The n-conductive tub structure is supplied with a higher voltage than the p-conductive semiconductor area and the p-conductive semiconductor substrate. The semiconductor substrate is put at a low supply voltage (VSS) and the tub structure at a high supply voltage, so that a voltage to be buffered is applied at the tub structure. The voltage to be buffered may be a negative word conductor blocking voltage or an amplified word conductor voltage.