LAYOUT AND WIRING SCHEME FOR MEMORY CELLS WITH VERTICAL TRANSISTORS

摘要

A memory device (10) having vertical transistors in accordance with the present invention includes an active area pad (12) isolated from adjacent active area pads (12) on all sides and having a set of trench capacitors (14) associated therewith. The set of trench capacitors (14) are coupled to the active area pad (12) through vertical transistors (22). The active area pad is configured to connect the set of trench capacitors to a first contact (16). A gate conductor pad (18) is disposed between a set of active area pads and adapted to activate at least one vertical transistor in each active area pad adjacent to the gate conductor pad. Each gate conductor pad is activated by a second contact (24) such that when the gate conductor pad is activated through the second contact the at least one vertical transistor in each active area pad conducts to provide access to the trench capacitors and transfers a state between the first contact and the trench capacitors.