SINGLE RAIL DOMINO LOGIC FOR FOUR-PHASE CLOCKING SCHEME

摘要

A single rail domino logic circuit (Figure 1) using a four-phase clocking scheme. A stacked PMOS pair (123, 125) provides a quarter clock cycle precharge time. The quarter clock cycle precharge time allows for placement of an additional inverter in the output signal (19) path to form both an output signal and a complement of the output signal (21) for use in subsequent logic stages.