| 摘要 |
<p>A circuit for processing signalling, e.g. system No. 7 (SS7) Layer 2, signalling associated with one or more time division multiplexed (TDM) data streams in which each data stream is shared between a plurality of data channels, in which each data channel is allocated a sequence of time slots in the data stream; and in which each time slot comprises a plurality of bits; in which operation of the circuit is synchronized to a clock signal and the circuit comprises means for processing one bit in one cycle of the clock signal. Advantageously, the circuit comprises processing means for processing SS7 Layer 2 messages, the processing means comprising a functional block for processing transmit and receive bits in successive operations. The circuit may comprise a PLD.</p> |
