| 摘要 |
PROBLEM TO BE SOLVED: To reduce the variation of delay fluctuations of LSI output data caused by LSI process variation, power supply voltage fluctuations, ambient temperature change or the like. SOLUTION: A feedback path to a PLL inputting part consists of a clock distribution circuit 11, a PLL feedback clock output buffer 21, a PLL feedback loop wiring 22 and a PLL feedback clock input buffer 20, and meanwhile, a data transfer path consists of a data output buffer 8 which is synchronized with a clock outputted from the circuit 11 and outputs it to an LSI on the next stage and a data wiring 14 which transfers data to the LSI on the next stage. |
