Apparatus and method for maintaining bit line charge state during a read operation

摘要

A keeper circuit (14) is included in a memory arrangement comprising a column of memory cells (20) connected by a bit line pair (16,18). The keeper circuit (14) comprises two keeper transistors. One keeper transistor (86) is connected to control current from a supply voltage source to one bit line (16) and the other keeper transistor (88) is connected to control current from the supply voltage source to the other bit line (18) of the bit line pair. Current through each keeper transistor (86, 88) is controlled by the charge state of the opposite bit line. A low charge state on one bit line causes the keeper transistor associated with the opposite bit line to conduct and maintain the charge level of the opposite bit line.