发明名称 |
Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections |
摘要 |
A method for making a novel structure having borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections on integrated circuits is achieved. An etch-stop layer and a planar insulating layer are formed over the devices on a substrate. Contact openings are etched in the insulating layer to the etch-stop layer and the etch-stop layer is removed over the N- contact areas. An N+ doped polysilicon layer is deposited, and second contact openings are etched in the polysilicon and insulating layers over N+ and P+ contacts on the substrate to the etch-stop layer. The etch-stop layer is selectively removed and a conducting barrier layer and a metal layer are deposited having a second etch-stop layer on the surface. The layers are patterned to form interconnecting lines and concurrently to form polysilicon landing plugs to the N- contacts, while forming metal landing plugs to the N+ and P+ contacts. Via holes can now be etched in a second insulating layer over and to the landing plugs. The polysilicon landing plugs to the N- contacts reduce current leakage, while the metal contacts to the N+ and P+ contacts reduce the contact resistance (Rc). The landing plugs protect the substrate contacts from damage during via hole etch and reduce the aspect ratio for making more reliable contacts.
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申请公布号 |
US6159839(A) |
申请公布日期 |
2000.12.12 |
申请号 |
US19990247977 |
申请日期 |
1999.02.11 |
申请人 |
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
JENG, ERIK S.;CHEN, BI-LING;HSIEH, CHIEN-SHENG |
分类号 |
H01L21/60;H01L21/768;H01L21/8242;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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