| 摘要 |
PROBLEM TO BE SOLVED: To provide a frequency controller that receives fluctuations in an input signal frequency before and after a mean value that gives no effect onto a clock signal extracted or synthesized, even when strong jitter is in existence in the input signal. SOLUTION: This frequency controller as a clock extract circuit EH in a communication terminal is provided with a phase and frequency comparator CPF and a voltage-controlled oscillator VCO. A 4-stage sampling circuit 1 and a phase comparator 2 in phase and frequency comparator CPF conduct phase comparison and a sampling circuit 1, a frequency comparator 3, a reversible counter 4 and a D/A converter 5 conduct frequency comparison. The phase and frequency comparator CPF compares the frequency of a signal Din with the frequency of a signal H to produce a variable voltage analog control signal VC to apply direct voltage control to the oscillator VCO, as a result, a clock signal H with a frequency set to the mean clock frequency of the data signal Din is produced. |
